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d a t a sh eet product speci?cation supersedes data of 1997 may 26 file under integrated circuits, ic22 1998 may 15 integrated circuits saa7111a enhanced video input processor (evip)
1998 may 15 2 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a contents 1 features 2 applications 3 general description 4 quick reference data 5 ordering information 6 block diagram 7 pinning 8 functional description 8.1 analog input processing 8.2 analog control circuits 8.2.1 clamping 8.2.2 gain control 8.3 chrominance processing 8.4 luminance processing 8.5 rgb matrix 8.6 vbi-data bypass 8.7 vpo-bus (digital outputs) 8.8 reference signals href, vref and cref 8.9 synchronization 8.10 clock generation circuit 8.11 power-on reset and ce input 8.12 rtco output 8.13 the line-21 text slicer 8.13.1 suggestions for i2c-bus interface of the display software reading line-21 data 9 boundary-scan test 9.1 initialization of boundary-scan circuit 9.2 device identification codes 10 gain charts 11 limiting values 12 characteristics 13 timing diagrams 14 clock system 14.1 clock generation circuit 14.2 power-on control 15 output formats 16 application information 16.1 layout hints 17 i 2 c-bus description 17.1 i 2 c-bus format 17.2 i 2 c-bus detail 17.2.1 subaddress 00 17.2.2 subaddress 02 17.2.3 subaddress 03 17.2.4 subaddress 04 17.2.5 subaddress 05 17.2.6 subaddress 06 17.2.7 subaddress 07 17.2.8 subaddress 08 17.2.9 subaddress 09 17.2.10 subaddress 0a 17.2.11 subaddress 0b 17.2.12 subaddress 0c 17.2.13 subaddress 0d 17.2.14 subaddress 0e 17.2.15 subaddress 10 17.2.16 subaddress 11 17.2.17 subaddress 12 17.2.18 subaddress 13 17.2.19 subaddress 15 17.2.20 subaddress 16 17.2.21 subaddress 17 17.2.22 subaddress 1a (read-only register) 17.2.23 subaddress 1b (read-only register) 17.2.24 subaddress 1c (read-only register) 17.2.25 subaddress 1f (read-only register) 18 filter curves 18.1 anti-alias filter curve 18.2 tuf-block filter curve 18.3 luminance filter curves 18.4 chrominance filter curves 19 i 2 c-bus start set-up 20 package outlines 21 soldering 21.1 introduction 21.2 reflow soldering 21.3 wave soldering 21.4 repairing soldered joints 22 definitions 23 life support applications 24 purchase of philips i 2 c components
1998 may 15 3 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 1 features four analog inputs, internal analog source selectors, e.g. 4 cvbs or 2 y/c or (1 y/c and 2 cvbs) two analog preprocessing channels fully programmable static gain for the main channels or automatic gain control for the selected cvbs or y/c channel switchable white peak control two built-in analog anti-aliasing filters two 8-bit video cmos analog-to-digital converters on-chip clock generator line-locked system clock frequencies digital pll for horizontal-sync processing and clock generation requires only one crystal (24.576 mhz) for all standards horizontal and vertical sync detection automatic detection of 50 and 60 hz field frequency, and automatic switching between pal and ntsc standards luminance and chrominance signal processing for pal bghi, pal n, pal m, ntsc m, ntsc n, ntsc 4.43, ntsc-japan and secam user programmable luminance peaking or aperture correction cross-colour reduction for ntsc by chrominance comb filtering pal delay line for correcting pal phase errors real time status information output (rtco) brightness contrast saturation (bcs) control on-chip the yuv (ccir-601) bus supports a data rate of: C 864 f h = 13.5 mhz for 625 line sources C 858 f h = 13.5 mhz for 525 line sources. data output streams for 16, 12 or 8-bit width with the following formats: C yuv4:1:1 (12-bit) C yuv4:2:2 (16-bit) C yuv4:2:2 (ccir-656) (8-bit) C rgb (5, 6, and 5) (16-bit) with dither C rgb (8, 8, and 8) (24-bit) with special application. odd/even field identification by a non interlace cvbs input signal fix level for rgb output format during horizontal blanking 720 active samples per line on the yuv bus one user programmable general purpose switch on an output pin built-in line-21 text slicer a 27 mhz vertical blanking interval (vbi) data bypass programmable by i 2 c-bus for intercast applications power-on control two via i 2 c-bus switchable outputs for the digitized cvbs or y/c input signals ad1 (7 to 0) and ad2 (7 to 0) chip enable function (reset for the clock generator and power save mode up from chip version 3) compatible with memory-based features (line-locked clock) boundary scan test circuit complies with the ieee std. 1149.1 - 1990 (id-cod e = 0 f111 02 b) i 2 c-bus controlled (full read-back ability by an external controller) low power ( < 0.5 w), low voltage (3.3 v), small package (lqfp64) 5 v tolerant digital i/o ports. 2 applications desktop/notebook (pcmcia) video multimedia digital television image processing video phone intercast.
1998 may 15 4 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 3 general description the enhanced video input processor (evip) is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and adc, an automatic clamp and gain control, a clock generation circuit (cgc), a digital multi-standard decoder (pal bghi, pal m, pal n, ntsc m, ntsc-japan ntsc n and secam), a brightness/contrast/saturation control circuit, a colour space matrix (see fig.1) and a 27 mhz vbi-data bypass. the pure 3.3 v cmos circuit saa7111a, analog front-end and digital video decoder, is a highly integrated circuit for desktop video applications. the decoder is based on the principle of line-locked clock decoding and is able to decode the colour of pal, secam and ntsc signals into ccir-601 compatible colour component values. the saa7111a accepts as analog inputs cvbs or s-video (y/c) from tv or vtr sources. the circuit is i 2 c-bus controlled. the saa7111a then supports several text features as line 21 data slicing and a high-speed vbi data bypass for intercast. 4 quick reference data 5 ordering information symbol parameter min. typ. max. unit v ddd digital supply voltage 3.0 3.3 3.6 v v dda analog supply voltage 3.1 3.3 3.5 v t amb operating ambient temperature 0 25 70 c p a+d analog and digital power - 0.5 - w type number package name description version saa7111ahz lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 saa7111ah qfp64 plastic quad ?at package; 64 leads (lead length 1.6 mm); body 14 14 2.7 mm sot393-1
1998 may 15 5 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 6 block diagram fig.1 block diagram. handbook, full pagewidth sda xtal xtali res iicsa trst tdi hs vs clock generation circuit power-on control interface i 2 c-bus synchronization circuit luminance circuit saa7111a chrominance circuit and brightness contrast saturation control vbi data bypass upsampling filter i 2 c-bus control clocks y 31 analog processing and analog-to- digital conversion ai11 ai12 ai21 ai22 12 10 8 6 ad2 ad1 analog control con bypass 30 27 17 29 28 60 15 16 24 rts0 55 54 21 22 20 llc2 cref 52 34 to 39 42 to 51 53 fei href vpo (0 : 15) gpsw 63 62 61 23 v sss n.c. n.c. 64 10 13 aout 14 rtco ce mgg061 rts1 llc v ssa0 v dda0 v ssd1-5 v ddd1-5 57,41,33,25,18 56,40,32,26,19 v ssa1-2 v dda1-2 9,5 11,7 y/cvbs c/cvbs tck 59 4 58 2 3 tms tdo vref yuv-to-rgb conversion and output formatter uv y processing y lfco test control block for boundary scan test and scan test scl
1998 may 15 6 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 7 pinning symbol pin i/o/p description (l)qfp64 n.c. 1 - do not connect. tdo 2 o test data output for boundary scan test; note 1. tdi 3 i test data input for boundary scan test; note 1. tms 4 i test mode select input for boundary scan test or scan test; note 1. v ssa2 5 p ground for analog supply voltage channel 2. ai22 6 i analog input 22. v dda2 7 p positive supply voltage for analog channel 2 (+3.3 v). ai21 8 i analog input 21. v ssa1 9 p ground for analog supply voltage channel 1. ai12 10 i analog input 12. v dda1 11 p positive supply voltage for analog channel 1 (+3.3 v). ai11 12 i analog input 11. v sss 13 p substrate ground connection. aout 14 o analog test output; for testing the analog input channels. v dda0 15 p positive supply voltage for internal clock generator circuit (cgc) (+3.3 v). v ssa0 16 p ground for internal cgc. vref 17 o vertical reference output signal (i 2 c-bit compo = 0) or inverse composite blanking signal (i 2 c-bit compo = 1) (enabled via i 2 c-bus bit oehv). v ddd5 18 p digital supply voltage 5 (+3.3 v). v ssd5 19 p ground for digital supply voltage 5. llc 20 o line-locked system clock output (27 mhz). llc2 21 o line-locked clock 1 2 output (13.5 mhz). cref 22 o clock reference output: this is a clock quali?er signal distributed by the internal cgc for a data rate of llc2. using cref all interfaces on the vpo bus are able to generate a bus timing with identical phase. if ccir 656 format is selected (ofts0 = 1 and ofts1 = 1) an inverse composite blanking signal (pixel quali?er) is provided on this pin. res 23 o reset output (active low); sets the device into a de?ned state. all data outputs are in high impedance state. the i 2 c-bus is reset (waiting for start condition). ce 24 i chip enable; connection to ground forces a reset, up from version 3 power save function additionally available. v ddd4 25 p digital supply voltage input 4 (+3.3 v). v ssd4 26 p ground for digital supply voltage input 4. hs 27 o horizontal sync output signal (programmable); the positions of the positive and negative slopes are programmable in 8 llc increments over a complete line (equals 64 m s) via i 2 c-bus bytes hsb and hss. fine position adjustment in 2 llc increments can be performed via i 2 c-bus bits hdel1 and hdel0. rts1 28 o two functions output; controlled by i 2 c-bus bit rtse1. rtse1 = 0: pal line identi?er (low = pal line); indicates the inverted and non-inverted r - y component for pal signals. rtse1 = 1: h-pll locked indicator; a high state indicates that the internal horizontal pll has locked.
1998 may 15 7 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a rts0 29 o two functions output; controlled by i 2 c-bus bit rtse0. rtse0 = 0: odd/even ?eld identi?cation (high = odd ?eld). rtse0 = 1: vertical locked indicator; a high state indicates that the internal vertical noise limiter (vnl) has locked. vs 30 o vertical sync signal (enabled via i 2 c-bus bit oehv); this signal indicates the vertical sync with respect to the yuv output. the high period of this signal is approximately six lines if the vnl function is active. the positive slope contains the phase information for a de?ection controller. href 31 o horizontal reference output signal (enabled via i 2 c-bus bit oehv); this signal is used to indicate data on the digital yuv bus. the positive slope marks the beginning of a new active line. the high period of href is 720 y samples long. href can be used to synchronize data multiplexer/demultiplexer. href is also present during the vertical blanking interval. v ssd3 32 p ground for digital supply voltage input 3. v ddd3 33 p digital supply voltage 3 (+3.3 v). vpo (15 to 10) 34 to 39 o digital vpo-bus (video port out) signal; higher bits of the 16-bit vpo-bus or the 16-bit rgb-bus output signal. the output data rate, the format and multiplexing scheme of the vpo-bus are controlled via i 2 c-bus bits ofts0 and ofts1. if i 2 c-bus bit vipb = 1 the six msbs of the digitized input signal are connected to these outputs, con?gured by the i 2 c-bus mode bits (see figs 33 to 40): luma ? vpo15 to vpo8, chroma ? vpo7 to vpo0. v ssd2 40 p ground for digital supply voltage input 2. v ddd2 41 p digital supply voltage 2 (+3.3 v). vpo (9 to 0) 42 to 51 o digital vpo-bus output signal; lower bits of the 16-bit yuv-bus or the 16-bit rgb-bus output signal. the output data rate, the format and multiplexing schema of the vpo-bus are controlled via i 2 c-bus bits ofts0 and ofts1. if i 2 c-bus bit vipb = 1 the digitized input signal are connected to these outputs, con?gured by the i 2 c-bus mode bits (see figs 33 to 40): luma ? vpo15 to vpo8, chroma ? vpo7 to vpo0. fei 52 i fast enable input signal (active low); this signal is used to control fast switching on the digital yuv-bus. a high at this input forces the ic to set its y and uv outputs to the high impedance state. gpsw 53 o general purpose switch output; the state of this signal is set via i 2 c-bus control and the levels are ttl compatible. xtal 54 o second terminal of crystal oscillator; not connected if external clock signal is used. xtali 55 i input terminal for 24.576 mhz crystal oscillator or connection of external oscillator with cmos compatible square wave clock signal. v ssd1 56 p ground for digital supply voltage input 1. v ddd1 57 p digital supply voltage input 1 (+3.3 v). trst 58 i test reset input not (active low), for boundary scan test; notes 1, 2 and 3. tck 59 i test clock for boundary scan test; note 1. rtco 60 o real time control output: contains information about actual system clock frequency, subcarrier frequency and phase and pal sequence. symbol pin i/o/p description (l)qfp64
1998 may 15 8 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a notes 1. in accordance with the ieee1149.1 standard the pads tck, tdi, tms and trst are input pads with an internal pull-up transistor and tdo a 3-state output pad. 2. this pin provides easy initialization of bst circuit. trst can be used to force the tap (test access port) controller to the test-logic-reset state (normal operation) at once. 3. for board design without boundary scan implementation (pin compatibility with the saa7110) connect the trst pin to ground. iicsa 61 i i 2 c-bus slave address select; 0 = 48h for write, 49h for read 1 = 4ah for write, 4bh for read. sda 62 i/o serial data input/output (i 2 c-bus). scl 63 i/o serial clock input/output (i 2 c-bus). n.c. 64 - not connect. symbol pin i/o/p description (l)qfp64
1998 may 15 9 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a fig.2 pin configuration (lqfp64/qfp64). handbook, full pagewidth saa7111a mgg060 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 tck iicsa sda rtco n.c. tdo tdi tms v ssa2 n.c. ai22 v dda2 vpo15 vpo14 vpo13 vpo12 vpo11 vpo10 vpo9 vpo8 vpo7 vpo6 vpo5 vpo4 vpo3 vpo2 vpo1 vpo0 fei gpsw xtal xtali v ssd1 v ddd1 v ddd3 v ddd2 v ssd2 ai21 ai11 aout v ssa1 v ssa0 v ssd5 llc llc2 cref ce hs rts1 rts0 vs href v ssd3 v ssd4 v ddd4 vref v sss v dda1 v dda0 v ddd5 ai12 scl trst res
1998 may 15 10 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 8 functional description 8.1 analog input processing the saa7111a offers four analog signal inputs, two analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video cmos adc (see fig.5). 8.2 analog control circuits the anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. during the vertical blanking time, gain and clamping control are frozen. 8.2.1 c lamping the clamp control circuit controls the correct clamping of the analog input signals. the coupling capacitor is also used to store and filter the clamping voltage. an internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. the clamping levels for the two adc channels are fixed for luminance (60) and chrominance (128). clamping time in normal use is set with the hcl pulse at the back porch of the video signal. 8.2.2 g ain control signal (white) peak control limits the gain at signal overshoots. the flow charts (see figs 13 and 14) show more details of the agc. the influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control. the gain control circuit receives (via the i 2 c-bus) the static gain levels for the two analog amplifiers or controls one of these amplifiers automatically via a built-in automatic gain control (agc) as part of the analog input control (aico). fig.3 analog line with clamp (hcl) and gain range (hsy). handbook, halfpage hcl mgl065 hsy analog line blanking tv line 1 60 255 gain clamp the agc (automatic gain control for luminance) is used to amplify a cvbs or y signal to the required signal amplitude, matched to the adcs input voltage range. the agc active time is the sync bottom of the video signal. 8.3 chrominance processing the 8-bit chrominance signal is fed to the multiplication inputs of a quadrature demodulator, where two subcarrier signals from the local oscillator dto1 are applied (0 and 90 phase relationship to the demodulator axis). the frequency is dependent on the present colour standard. the output signals of the multipliers are low-pass filtered (four programmable characteristics) to achieve the desired bandwidth for the colour difference signals (pal and ntsc) or the 0 and 90 fm-signals (secam). the colour difference signals are fed to the brightness/contrast/saturation block (bcs), which includes the following five functions: agc (automatic gain control for chrominance pal and ntsc) chrominance amplitude matching (different gain factors for r - y and b - y to achieve ccir-601 levels cr and cb for all standards) chrominance saturation control luminance contrast and brightness limiting yuv to the values 1 (min.) and 254 (max.) to fulfil ccir-601 requirements. fig.4 automatic gain range. handbook, halfpage analog input level controlled adc input level maximum minimum range tbf 0 db 0 db mgg063 + 4.5 db - 7.5 db (1 v(p-p) 27/47 w )
1998 may 15 11 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a the secam-processing contains the following blocks: baseband bell filters to reconstruct the amplitude and phase equalized 0 and 90 fm-signals phase demodulator and differentiator (fm-demodulation) de-emphasis filter to compensate the pre-emphasised input signal, including frequency offset compensation (db or dr white carrier values are subtracted from the signal, controlled by the secam-switch signal). the burst processing block provides the feedback loop of the chroma pll and contains; burst gate accumulator colour identification and killer comparison nominal/actual burst amplitude (pal/ntsc standards only) loop filter chrominance gain control (pal/ntsc standards only) loop filter chrominance pll (only active for pal/ntsc standards) pal/secam sequence detection, h/2-switch generation increment generation for dto1 with divider to generate stable subcarrier for non-standard signals. the chrominance comb filter block eliminates crosstalk between the chrominance channels in accordance with the pal standard requirements. for ntsc colour standards the chrominance comb filter can be used to eliminate crosstalk from luminance to chrominance (cross-colour) for vertical structures. the comb filter can be switched off if desired. the embedded line delay is also used for secam recombination (cross-over switches). the resulting signals are fed to the variable y-delay compensation, rgb matrix, dithering circuit and output interface, which contains the vpo output formatter and the output control logic (see fig.6). 8.4 luminance processing the 8-bit luminance signal, a digital cvbs format or a luminance format (s-vhs, hi8), is fed through a switchable prefilter. high frequency components are emphasized to compensate for loss. the following chrominance trap filter (f 0 = 4.43 or 3.58 mhz centre frequency selectable) eliminates most of the colour carrier signal, therefore, it must be bypassed for s-video (s-vhs and hi8) signals. the high frequency components of the luminance signal can be peaked (control for sharpness improvement via i 2 c-bus) in two band-pass filters with selectable transfer characteristic. this signal is then added to the original (unpeaked) signal. a switchable amplifier achieves common dc amplification, because the dc gains are different in both chrominance trap modes. the improved luminance signal is fed to the bcs control located in the chrominance processing block (see fig.7). 8.5 rgb matrix y, cr and cb data are converted after interpolation into rgb data in accordance with ccir-601 recommendations. the realized matrix equations consider the digital quantization: r = y + 1.371 cr g=y - 0.336 cb - 0.698 cr b = y + 1.732 cb. after dithering (noise shaping) the rgb data is fed to the output interface within the vpo-bus output formatter. 8.6 vbi-data bypass for a 27 mhz vbi-data bypass the offset binary cvbs signal is upsampled behind the adcs. upsampling of the cvbs signal from 13.5 to 27 mhz is possible, because the adcs deliver high performance at 13.5 mhz sample clock. suppressing of the back folded cvbs frequency components after upsampling is achieved by an interpolation filter (see fig.42). the tuf block on the digital top level performs the upsampling and interpolation for the bypassed cvbs signal (see fig.6). for bypass details see figs 8 to 10. 8.7 vpo-bus (digital outputs) the 16-bit vpo-bus transfers digital data from the output interfaces to a feature box or a field memory, a digital colour space converter (saa7192 dcsc), a video enhancement and digital-to-analog processor (saa7165 veda2) or a colour graphics board (targa-format) as a graphical user interface.
1998 may 15 12 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a the output data formats are controlled via the i 2 c-bus bits ofts0, ofts1 and rgb888. timing for the data stream formats, yuv (4 : 1 : 1) (12-bit), yuv (4 : 2 : 2) (16-bit), rgb (5, 6 and 5) (16-bit) and rgb (8, 8 and 8) (24-bit) with an llc2 data rate, is achieved by marking each second positive rising edge of the clock llc in conjunction with cref (clock reference) (except rgb (8, 8 and 8), see special application in fig.32). the higher output signals vpo15 to vpo8 in the yuv format perform the digital luminance signal. the lower output signals vpo7 to vpo0 in the yuv format are the bits of the multiplexed colour difference signals (b - y) and (r - y). the arrangement of the rgb (5, 6 and 5) and rgb (8, 8 and 8) data stream bits on the vpo-bus is given in table 6. the data stream format yuv 4:2:2 (the 8 higher output signals vpo15 to vpo8) in llc data rate fulfils the ccir-656 standard with its own timing reference code at the start and end of each video data block. a pixel in the format tables is the time required to transfer a full set of samples. if 16-bit 4 : 2 : 2 format is selected two luminance samples are transmitted in comparison to one (b - y) and one (r - y) sample within a pixel. the time frames are controlled by the href signal. fast enable is achieved by setting input fei to low. the signal is used to control fast switching on the digital vpo-bus. high on this pin forces the vpo outputs to a high-impedance state (see figs 18 and 19). the i 2 c-bus bit oeyc has to be set high to use this function. the digitized pal, secam or ntsc signals ad1 (7 to 0) and ad2 (7 to 0) are connected directly to the vpo-bus via i 2 c-bus bit vipb = 1 and mode = 4, 5, 6 or 7. ad1 (7 to 0) ? vpo (15 to 8) and ad2 (7 to 0) ? vpo (7 to 0). the selection of the analog input channels is controlled via i 2 c-bus subaddress 02 mode select. the upsampled 8-bit offset binary cvbs signal (vbi-data bypass) is multiplexed under control of the i 2 c-bus to the digital vpo-bus (see fig.8). 8.8 reference signals href, vref and cref href: the positive slope of the href output signal indicates the beginning of a new active video line. the high period is 720 luminance samples long and is also present during the vertical blanking. the description of timing and position from href is illustrated in figs 15, 16, 21 and 23. vref: the vref output delivers a vertical reference signal or an inverse composite blank signal controlled via the i 2 c-bus [subaddress 11, inverse composite blank (compo)]. furthermore four different modes of vertical reference signals are selectable via the i 2 c-bus [subaddress 13, vertical reference output control (vctr1 and vctr0)]. the description of vref timing and position is illustrated in figs 15, 16, 24 and 25. cref: the cref output delivers a clock/pixel qualifier signal for external interfaces to synchronize to the vpo-bus data stream. four different modes for the clock qualifier signal are selectable via the i 2 c-bus [subaddress 13, clock reference output control (cctr1 and cctr0)]. the description of cref timing and position is illustrated in figs 16, 18, 20 and 21. 8.9 synchronization the prefiltered luminance signal is fed to the synchronization stage. its bandwidth is reduced to 1 mhz in a low-pass filter. the sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. the resulting output signal is applied to the loop filter to accumulate all phase deviations. internal signals (e. g. hcl and hsy) are generated in accordance with analog front-end requirements. the output signals hs, vs, and plin are locked to the timing reference, guaranteed between the input signal and the href signal, as further improvements to the circuit may change the total processing delay. it is therefore not recommended to use them for applications which require absolute timing accuracy on the input signals. the loop filter signal drives an oscillator to generate the line frequency control signal lfco (see fig.7). 8.10 clock generation circuit the internal cgc generates all clock signals required for the video input processor. the internal signal lfco is a digital-to-analog converted signal provided by the horizontal pll. it is the multiple of the line frequency internally the lfco signal is multiplied by a factor of 2 or 4 in the pll circuit (including phase detector, loop filtering, vco and frequency divider) to obtain the llc and llc2 output clock signals. the rectangular output clocks have a 50% duty factor (see fig.26). 6.75mhz 429 432 --------- - f h =
1998 may 15 13 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 8.11 power-on reset and ce input a missing clock, insufficient digital or analog v dda0 supply voltages (below 2.7 v) will initiate the reset sequence; all outputs are forced to 3-state. the indicator output res is low for approximately 128llc after the internal reset and can be applied to reset other circuits of the digital tv system. it is possible to force a reset by pulling the chip enable (ce) to ground. after the rising edge of ce and sufficient power supply voltage, the outputs llc, llc2, cref, rtco, rts0, rts1, gpsw and sda return from 3-state to active, while href, vref, hs and vs remain in 3-state and have to be activated via i 2 c-bus programming (see table 5). 8.12 rtco output the real time control and status output signal contains serial information about the actual system clock (increment of the hpll), subcarrier frequency [increment and phase (via reset) of the fsc-pll] and pal sequence bit. the signal can be used for various applications in external circuits, e.g. in a digital encoder to achieve clean encoding (see fig.20). 8.13 the line-21 text slicer the text slicer block detects and acquires line-21 closed captioning data from a 525-line cvbs signal. extended data services on line-21 field 2 are also supported. if valid data is detected the two data bytes are stored in two i 2 c-bus registers. a parity check is also performed and the result is stored in the msb of the corresponding byte. a third i 2 c-bus register is provided for data valid and data ready flags. the two bits f1val and f2val indicate that the input signal carries valid closed captioning data in the corresponding fields. the data ready bits f1rdy and f2rdy have to be evaluated if asynchronous i 2 c-bus reading is used. 8.13.1 s uggestions for i 2 c- bus interface of the display software reading line -21 data there are two methods by which the software can acquire the data: 1. synchronous reading once per frame (or once per field); it can use either the rising edge (line-21 field 1) or both edges (line-21 field 1 or 2) of the odd signal (pin rtso) to initiate an i 2 c-bus read transfer of the three registers 1a, 1b and 1c. 2. asynchronous reading; it can poll either the f1rdy bit (line-21 field 1) or both f1rdy/f2rdy bits (line-21 field 1 or 2). after valid data has been read the corresponding f*rdy bit is set to low until new data has arrived. the polling frequency has to be slightly higher than the frame or field frequency, respectively.
1998 may 15 14 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth ai22 ai21 fuse (1 : 0) ai12 ai11 fuse (1 : 0) aosl (1 : 0) holdg analog control gai10-gai18 v sss n.c. vbsl 8 8 64 13 mgc655 14 chr lum vertical blanking control source switch clamp circuit analog amplifier anti-alias filter bypass switch source switch clamp circuit analog amplifier anti-alias filter bypass switch adc2 adc1 test and selector clamp control gain control cross multiplexer anti-alias control v dda1 v ssa2 aout mode control mode 0 mode 1 mode 2 gai20-gai28 gudl0-gudl2 gafix wpoff hsy vblnk svref hcl ad1byp ad2byp buffer dac9 dac9 hlnrs uptcv v dda2 9 5 6 8 11 7 10 12 v ssa1 glimb glimt wipa sltca fig.5 analog input processing.
1998 may 15 15 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... fig.6 chrominance circuit. g ewidth chr lum code ad1byp ad2byp brig cont satn huec dccf f h /2 switch signal mgg062 v ddd1-5 v ssd1-5 57,41,33, 25,18 56,40,32,26,19 31 60 34 to 39 42 to 51 52 quadrature demodulator comb filters secam recombination formatter output and interface accumulator burst gate low-pass loop filter subcarrier increment generation and divider subcarrier generation fctc cstd 1 rgb matrix interpolation dithering secam processing dit cbr chbw0 chbw1 cstd 0 incs res tck tdi 59 3 23 power-on control test control block tdo trst 2 58 tms 4 lum y rtco n.c. 1 clocks ce y sequential uv signals uv rgb fei href vpo (9 : 0) vpo (15 : 10) vbi data bypass tuf phase demodulator amplitude detector ofts0 ofts1 rgb888 oeyc oehv feco vrln vsta (8 : 0) vsto (8 : 0) gpsw rtse1 rtse0 vipb vlof colo compo level adjustment, brightness, contrast, and saturation control gain control and y-delay compensation
1998 may 15 16 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth cref llc xtali xtal vref rts0 hs vs sda scl iicsa gpsw i c bus control clocks synchronization circuit pref byps aper0 aper1 vblb aufd hsb hss fsel vtrc sttc fidt vnoi0 vnoi1 vtrc vtrc ce rts1 mgc654 llc2 hlck v dda0 v ssa0 53 61 63 62 30 29 17 27 28 16 24 15 54 55 22 20 21 dac6 and weighting adding band-pass variable filter chrominance trap prefilter amplifier matching clock line-locked generator 2 loop filter detector phase coarse detector phase fine sync slicer sync prefilter line 21 text slicer clock crystal generator time discrete oscillator 2 interface i c-bus processor vertical counter generation clock circuit luminance circuit bpss0 bpss1 pref lum vblb vblb y clock circuit incs stage hpll vtrc exfil byte1 byte2 status 2 2 fig.7 luminance and sync processing.
1998 may 15 17 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a fig.8 multiplexing of the cvbs signal to the vpo-bus. hrefint = internal horizontal reference. tbp = upsampled cvbs input data (27 mhz). ad1byp/ad2byp = digitized cvbs input data and y/c input data (13.5 mhz). vbp0 = programmable vertical reference signal. vbp4 = delayed programmable vertical reference signal (4llc clocks delay). handbook, full pagewidth mgg064 clock 0 hrefint v_gate (programmable) 4 reg clock 0 reg bchi1 bchi0 swhi 0 0 1 1 0 1 0 1 1 0 vbp0 vbp4 vbp0 ad1byp vbp4 0 mux cvbs up 1 0 mux byp up register 1 bclo1 bclo0 swlo 0 0 1 1 0 1 0 1 1 bclo1 to 0 i 2 c-bus bchi1 to 0 i 2 c-bus vipb i 2 c-bus tbp7 to 0 (cvbs) uv or yuv y or yuv 0 vbp0 vbp4 vbp0 vbp4 vbp0 ad2byp vbp4 0 mux cvbs up 1 0 vpo7 to 0 swhi swlo vpo15 to 8 mux byp up register 1 en (luma see fig. 37) (chroma see fig. 37)
1998 may 15 18 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a fig.9 vref output signal generation. vref_ccir 656 = vertical reference signal referring to the field interval definitions of ccir656. hrefint = internal horizontal reference signal. vrefint = internal vertical reference signal. vbp0 = programmable vertical reference signal. vbp4 = delayed programmable vertical reference signal (4llc clocks delay). handbook, full pagewidth mgg065 v c t r 1 0 0 1 1 0 1 0 1 v c t r 0 vrefint vref clock 0 compo vctr1 to 0 vrefout vref ccir 656 vbp0 vbp4 vbp0 vbp4 vrefint hrefint hrefint vref ccir 656 reg href clk0 reg clock 0 reg en 0 mux 1 clock 0 reg en fig.10 cref output signal generation. crefint = internal clock qualifier signal. handbook, full pagewidth mgg066 c c t r 1 0 0 1 1 0 1 0 1 c c t r 0 crefint crefint selected vref cctr1 to 0 cref clock 0 crefout 0 if vref = 0 1 if vref = 0 1 (always high) reg
1998 may 15 19 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 9 boundary-scan test the saa7111a has built in logic and 5 dedicated pins to support boundary-scan testing which allows board testing without special hardware (nails). the saa7111a follows the ieee std. 1149.1 - standard test access port and boundary-scan architecture set by the joint test action group (jtag) chaired by philips. the 5 special pins are test mode select (tms), test clock (tck), test reset (trst), test data input (tdi) and test data output (tdo). the bst functions bypass, extest, intest, sample, clamp and idcode are all supported (see table 1). details about the jtag bst-test can be found in the specification eee std. 1149.1 . a file containing the detailed boundary-scan description language (bsdl) description of the saa7111a is available on request. 9.1 initialization of boundary-scan circuit the test access port (tap) controller of an ic should be in the reset state (test_logic_reset) when the ic is in functional mode. this reset state also forces the instruction register into a functional instruction such as idcode or bypass. to solve the power-up reset, the standard specifies that the tap controller will be forced asynchronously to the test_logic_reset state by setting the trst pin low. 9.2 device identi?cation codes a device identification register (dir) is specified in ieee std. 1149.1-1990 - ieee standard test access port and boundary-scan architecture (ieee std. 1149.1b-1994). it is a 32-bit register which contains fields for the specification of the ic manufacturer, the ic part number and the ic version number. its biggest advantage is the possibility to check for the correct ics mounted after production and determination of the version number of ics during field service. when the idcode instruction is loaded into the bst instruction register, the identification register will be connected between tdi and tdo of the ic. the identification register will load a component specific code during the capture_data_register state of the tap controller and this code can subsequently be shifted out. at board level this code can be used to verify component manufacturer, type and version number. the device identification register contains 32-bits, numbered 31 to 0, where bit 31 is the most significant bit (msb) (nearest to tdi) and bit 0 is the least significant bit (lsb) (nearest to tdo); see fig.11. table 1 bst instructions supported by the saa7111a instruction description bypass this mandatory instruction provides a minimum length serial path (1 bit) between tdi and tdo when no test operation of the component is required. extest this mandatory instruction allows testing of off-chip circuitry and board level interconnections. sample this mandatory instruction can be used to take a sample of the inputs during normal operation of the component. it can also be used to preload data values into the latched outputs of the boundary-scan register. clamp this optional instruction is useful for testing when not all ics have bst. this instruction addresses the bypass register while the boundary-scan register is in external test mode. idcode this optional instruction will provide information on the components manufacturer, part number and version number. intest this optional instruction allows testing of the internal logic (no support for customers available). user1 this private instruction allows testing by the manufacturer (no support for customers available).
1998 may 15 20 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a fig.11 32 bits of identification code . handbook, full pagewidth mgl111 00000010101 1111000100010001 0010 4-bit version code 16-bit part number 11-bit manufacturer indentification tdi tdo 31 msb lsb 28 27 12 11 1 0 1
1998 may 15 21 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 10 gain charts fig.12 amplifier curve. handbook, halfpage 0 7.5 5.5 db 3.5 1.5 - 0.5 - 4.5 - 2.5 256 512 gain value (i) mgc648 bit [8] = 1 factor db = 20 x log 10 gain = ( 512 768 - i i > 256 bit [8] = 0 factor db = 20 x log 10 gain = ( 512 257 + i ( i < 256 ( fig.13 clamp and gain flow. wipe = white peak level (254); sbot = sync bottom level (1); cll = clamp level [60 y (128 c)]; hsy = horizontal sync pulse; hcl = horizontal clamp pulse. handbook, full pagewidth 10 + clamp - clamp no clamp 10 10 01 10 mgc647 fast - gain slow + gain + gain - gain hcl hsy adc sbot wipe cll analog input gain -> <- clamp vblk no blanking active 10
1998 may 15 22 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a fig.14 gain flow chart. x = system variable; y = iagv - fgvi > gudl; vblk = vertical blanking pulse; hsy = horizontal sync pulse; agv = actual gain value; fgv = frozen gain value. handbook, full pagewidth analog input amplifier anti-alias filter adc luma/chroma decoder x hsy >254 >254 <1 <4 >248 x = 0 x = 1 - 1/llc2 + 1/llc2 - 1/llc2 + / - 0 + 1/f + 1/l gain accumulator (18 bits) actual gain value 9-bit (agv) [ - 6/ + 6 db] x stop hsy y update fgv mgc652 agv gain value 9-bit 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 vblk 1 0 no action 9 8 dac gain holdg
1998 may 15 23 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 11 limiting values in accordance with the absolute maximum rating system (iec 134); all ground pins connected together and all supply pins connected together. note 1. human body model: equivalent to discharging a 100 pf capacitor through a 1.5 k w resistor. 12 characteristics v ddd = 3.0 to 3.6 v; v dda = 3.1 to 3.5 v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit v ddd digital supply voltage - 0.5 +4.6 v v dda analog supply voltage - 0.5 +4.6 v v i(a) input voltage at analog inputs - 0.5 v dda + 0.5 (4.6 max.) v v o(a) output voltage at analog output - 0.5 v dda + 0.5 v v i(d) input voltage at digital inputs and outputs outputs in 3-state - 0.5 +5.5 v v o(d) output voltage at digital outputs outputs active - 0.5 v ddd + 0.5 v d v ss voltage difference between v ssaall and v ssall - 100 mv t stg storage temperature - 65 +150 c t amb operating ambient temperature 0 70 c t amb(bias) operating ambient temperature under bias - 10 +80 c v esd electrostatic discharge all pins note 1 - 2000 +2000 v symbol parameter conditions min. typ. max. unit supplies v ddd digital supply voltage 3.0 3.3 3.6 v i ddd digital supply current - 63 70 ma p d digital power - 0.21 - w v dda analog supply voltage 3.1 3.3 3.5 v i dda analog supply current aosl = [1:0] = 00b; aout not connected - 52 - ma p a analog power - 0.17 - w p a+d analog and digital power - 0.38 - w p pd analog and digital power in power-down mode ce connected to ground (since version 3) - 0.02 - w analog part i clamp clamping current v i = 0.9 v dc - 3.5 -m a v i(p-p) input voltage (peak-to-peak value) for normal video levels [1 v (p-p)]; - 3db termination 27/47 w and ac coupling required; coupling capacitor = 22 nf 0.3 0.7 1.2 v |z i | input impedance clamping current off 200 -- k w c i input capacitance -- 10 pf
1998 may 15 24 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a a cs channel crosstalk f i = 5 mhz --- 50 db analog-to-digital converters b bandwidth at - 3db - 7 - mhz f diff differential phase (ampli?er plus anti-alias ?lter = bypass) - 2 - deg g diff differential gain (ampli?er plus anti-alias ?lter = bypass) - 2 - % f clkadc adc clock frequency 12.8 - 14.3 mhz dle dc differential linearity error - 0.7 - lsb ile dc integral linearity error - 1 - lsb digital inputs v il(scl,sda) low level input voltage pins sda and scl - 0.5 - +0.3v ddd v v ih high level input voltage pins sda and scl 0.7v ddd - v ddd + 0.5 v v il(xtal) low level cmos input voltage pin xtali - 0.3 - +0.8 v v ih(xtal) high level cmos input voltage pin xtali 2.0 - v ddd + 0.3 v v iln low level input voltage all other inputs - 0.3 - +0.8 v v ihn high level input voltage all other inputs 2.0 - 5.5 v i li input leakage current -- 1 m a c i input capacitance outputs at 3-state -- 8pf c i(n) input capacitance all other inputs -- 5pf digital outputs v ol(scl,sda) low level output voltage pins sda and scl sda/scl at 3 ma (6 ma) sink current -- 0.4 (0.6) v v ol low level output voltage v ddd = max; i ol =2ma 0 - 0.4 v v oh high level output voltage v ddd = min, i oh = - 2 ma 2.4 - v ddd + 0.5 v v ol(clk) low level output voltage for clocks - 0.5 - +0.6 v v oh(clk) high level output voltage for clocks 2.4 - v ddd + 0.5 v i lo output leakage current at 3-state mode -- 10 m a fei input timing t su;dat input data set-up time 13 -- ns t hd;dat input data hold time 3 -- ns symbol parameter conditions min. typ. max. unit
1998 may 15 25 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a data and control output timing; note 1 c l output load capacitance 15 - 40 pf t ohd;dat output hold time c l =15pf 4 -- ns t pd propagation delay c l =25pf -- 20 ns t pdz propagation delay to 3-state -- 20 ns clock output timing (llc and llc2); note 2 c l(llc) output load capacitance 15 - 40 pf t cy cycle time llc 35 - 39 ns llc2 70 - 78 ns d llc duty factors for t llch /t llc and t llc2h /t llc2 c l =25pf 40 - 60 % t r rise time llc, llc2 -- 5ns t f fall time llc, llc2 -- 5ns t d delay time llc output to llc2 output at 1.5 v; llc/llc2 = 25 pf - 4 - +8 ns data quali?er output timing (cref) t ohd;cref output hold time c l =15pf 4 -- ns t pd;cref propagation delay from positive edge of llc c l =25pf -- 20 ns clock input timing (xtali) d xtali duty factor for t xtalih /t xtali nominal frequency 40 - 60 % horizontal pll f hn nominal line frequency 50 hz ?eld - 15625 - hz 60 hz ?eld - 15734 - hz d f h /f hn permissible static deviation -- 5.7 % subcarrier pll f scn nominal subcarrier frequency pal bghi - 4433619 - hz ntsc m; ntsc-japan - 3579545 - hz pal m - 3575612 - hz pal n - 3582056 - hz d f sc lock-in range 400 -- hz crystal oscillator f n nominal frequency 3rd harmonic; note 3 - 24.576 - mhz d f/f n permissible nominal frequency deviation -- 50 10 - 6 symbol parameter conditions min. typ. max. unit
1998 may 15 26 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a notes 1. the levels must be measured with load circuits; 1.2 k w at 3 v (ttl load); c l = 50 pf. 2. the effects of rise and fall times are included in the calculation of t ohd;dat , t pd and t pdz . timings and levels refer to drawings and conditions illustrated in figs 15 and 16. 3. order number: philips 4322 143 05291. table 2 processing delay note 1. digital processing delay (llc clocks) for vbi data is defined in fig.23 horizontal timing diagram. crystal oscillator f n nominal frequency 3rd harmonic; note 3 - 24.576 - mhz d f/f n permissible nominal frequency deviation -- 50 10 - 6 d tf/f n permissible nominal frequency deviation with temperature -- 20 10 - 6 c rystal specification (x1) t amb(x1) operating ambient temperature 0 - 70 c c l load capacitance 8 -- pf r s series resonance resistor - 40 80 w c 1 motional capacitance - 1.5 20% - ff c 0 parallel capacitance - 3.5 20% - pf function typical analog delay ai22 ? adcin (aout) (ns) digital delay adcin ? vpo (llc clocks) [ydel(2 to 0) = 000]; note 1 without ampli?er or anti-alias ?lter 15 179 with ampli?er, without anti-alias ?lter 25 with ampli?er and anti-alias ?lter 75 symbol parameter conditions min. typ. max. unit
1998 may 15 27 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 13 timing diagrams fig.15 clock/data timing (8-bit ccir-656 format of the vpo-bus). an explanation of the output formats is given in table 6. handbook, full pagewidth 2.4 v t llc t f t pd t ohd;dat t llcl t llch outputs vpo, href, vref, vs, hs clock output llc t r 0.6 v 2.6 v 1.5 v 0.6 v mgc658 fig.16 clock/data timing (12 and 16-bit ccir-601 format of the vpo-bus). an explanation of the output formats is given in table 6. the fei timing of the vpo-bus is illustrated in figs 18 and 19. handbook, full pagewidth 2.4 v 0.6 v t llc t f t pd t ohd;cref t dllc2 t r t llcl t llch 2.4 v 0.6 v outputs vpo, href, clock output llc clock output llc2 1.5 v 0.6 v 2.6 v 1.5 v 0.6 v 2.6 v vref, vs, hs output cref t ohd;dat t dllc2 t pd mgc659 t llc t pd t ohd;cref
1998 may 15 28 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a fig.17 clock/data timing for rgb (8, 8 and 8) output format. an explanation of the output formats is given in table 6. handbook, full pagewidth mbh227 2.4 v 1.5 v 0.6 v 2.4 v 1.5 v 0.6 v 2.4 v 1.5 v 0.6 v clock output llc output cref rgb (8, 8, 8) data vpo15 to vpo8 rgb (8, 8, 8) data vpo7 to vpo0 2.4 v 1.5 v 0.6 v t ohd;dat t ohd;dat t ohd;cref t ohd;cref t ohd;cref t pd;cref t pd t pd;cref r(7 : 3) g(7 : 5) g(4 : 2) b(7 : 3) r(2 : 0) g(1 : 0) b(2 : 0) t llcl t llc t llc t f t r t llch fig.18 fei timing diagram ( fei sampling at cref = high) for ofts = 0, 1 or 2). i 2 c-bus bit feco = 1. handbook, full pagewidth llc cref href fei vpo to 3-state from 3-state mgc656 t pdz t pd t hd;dat t su;dat t ohd;dat
1998 may 15 29 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a fig.19 fei timing diagram ( fei sampling at cref = low) for ofts = 0, 1 or 2). timing is compatible with saa7110; i 2 c-bus bit feco = 0. handbook, full pagewidth llc cref href vpo t su;dat t hd;dat to 3-state mgc657 from 3-state t ohd;dat t pd t pdz fei fig.20 real time control output. (1) set to zero for one transmission, if a phase reset of the f sc - dto is applied via i 2 c-bus bit cdto. rtco sequence is generated in llc/4. the hpll increment represents the actual lfco frequency (f lfco 4=f llc ); 16 lsb from 20, upper four bits are fixed to 0100b. where: f xtal = 24.576 mhz, word length dto2 = 20 bits. the f sc increment represents the actual subcarrier frequency (related to the actual clock); 23 lsb from 24, msb is 0b. where: word length dto1 = 24 bits. f lfco incr hpll f xtal 2 word length dto2 ------------------------------------------------ - = f sc incr fscpll f xtal 2 word length dto1 ------------------------------------------------------- incr hpll 2 19 ---------------------------- = handbook, full pagewidth time slot: bit no.: transmitted once per line 22 1 21 19 20 15 16 17 18 7 8 9 11 10 12 13 14 sequence 19 0 67 2 3 6 4 5 2 3 0 16 45 reserved 16 incr fscpll mgc649 63 0 1 reserved 128 high low 15 incr hpll reserved 1 68 dto reset (1) 50 hz fields: 235 60 hz fields: 232
1998 may 15 30 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a fig.21 href timing diagram. handbook, full pagewidth 0 llc cref llc2 href yn uvn href yn uvn 1234 u0 v0 u2 v2 u4 end of active line start of active line 719 718 717 716 715 u718 v718 mgc646 v716 u716 v714 fig.22 fei timing in ccir 656 mode [ofts (1 : 0) = 3]. handbook, full pagewidth mbh766 t pd t pdz t ohd t hd t su llc fei vpo
1998 may 15 31 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a fig.23 horizontal timing diagram. (1) plin is switched to output rts1 via i 2 c-bus bit rtse1 = 0. (2) see table 2. (3) hdel (1 : 0) = 0 0, ydel (2 : 0) = 0 0 0. handbook, full pagewidth 0 108 - 107 107 - 106 mgd701 cvbs vbi 26 1/llc 179 1/llc 27 2/llc y - output href (50 hz) 12 2/llc 720 2/llc 144 2/llc 23 2/llc 138 2/llc 720 2/llc burst burst rts1 (plin) (1) processing delay cvbs->vpo (2) 0 0 4/llc href (60 hz) hs (60 hz) sync clipped 16 2/llc hs (50 hz) programming range (step size: 8/llc) hs (60 hz) programming range (step size: 8/llc) hs 43 2/llc
1998 may 15 32 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a fig.24 vertical timing diagram for 50 hz [nominal input signal vnl in normal mode (vnoi = 00b)]. (1) odd is switched to output rts0 via i 2 c-bus bit rtse0 = 0. (2) additional vref positions can be achieved via i 2 c-bits vctr1 and vctr0 (see fig.9). the luminance peaking and the chrominance trap are bypassed during vref = 0 if i 2 c-bus bit vblb is set to logic 1. the chrominance delay line (chrominance-comb filter for ntsc, phase error correcting for pal) is disabled during vref = 0. handbook, full pagewidth 313 314 315 316 317 318 319 335 336 1234567822 625 href input cvbs (b) 2nd field (a) 1st field vref vref vref vref vrln = 1 (2) vrln = 0 (2) 624 623 622 23 href input cvbs 312 311 310 vrln = 0 (2) 337 mgg069 535 x 2/llc vs rts0 (odd) (1) rts0 (odd) (1) 320 vs 77 x 2/llc vrln = 1 (2)
1998 may 15 33 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a fig.25 vertical timing diagram for 60 hz [nominal input signal vnl in normal mode (vnoi = 00b)]. (1) odd is switched to output rts0 via i 2 c-bus bit rtse0 = 0. (2) line numbers in parenthesis refer to ccir line counting. (3) additional vref positions can be achieved via i 2 c-bus bits vctr1 and vctr0 (see fig.9). the luminance peaking and the chrominance trap are bypassed during vref = 0 if i 2 c-bus bit vblb is set to logic 1. the chrominance delay line (chrominance-comb filter for ntsc, phase error correcting for pal) is disabled during vref = 0. handbook, full pagewidth vs (266) (267) (268) (269) (270) (271) (272) (273) (274) (4) (5) (6) (7) (8) (9) (10) (11) (20) (3) href (b) 2nd field (a) 1st field input cvbs (2) (1) (525) (21) (22) (283) (284) (265) (264) (263) (262) vrln = 1 (3) vrln = 0 (3) vrln = 1 (3) vrln = 0 (3) 1234567 8 17 525 524 523 522 18 19 263 264 265 266 267 268 269 270 271 280 281 262 261 260 259 (285) 282 (2) (2) mgg070 520 x 2/llc rts0 (odd) (1) 81 x 2/llc vref vref vref vref vs href input cvbs rts0 (odd) (1)
1998 may 15 34 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a table 3 digital output control note 1. only active in 656-format (ofts = 3). oeyc fei tclo (1) vpo 15 to 8 vpo 7to0 000 z 1 0 0 active 010 z 110 z 001zz 1 0 1 active z 011zz 111zz 14 clock system 14.1 clock generation circuit the internal cgc generates the system clocks llc, llc2 and the clock reference signal cref. the internally generated lfco (triangular waveform) is multiplied by 4 via the analog pll (including phase detector, loop filter, vco and frequency divider). the rectangular output signals have a 50% duty factor. table 4 clock frequencies clock frequency (mhz) xtal 24.576 llc 27 llc2 13.5 llc4 6.75 llc8 3.375 fig.26 block diagram of clock generation circuit. handbook, full pagewidth band pass fc = llc/4 zero cross detection phase detection loop filter divider 1/2 divider 1/2 oscillator delay cref mgc632 llc2 llc lfco
1998 may 15 35 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 14.2 power-on control power-on reset is activated at power-on, chip enable, pll clock generation failure and if the supply voltage falls below 2.7 v. the res signal can be applied to reset other circuits of the digital picture processing system. fig.27 power-on control circuit. ce = chip enable input; xtal = crystal oscillator output; llcint = internal system clock; resint = internal reset; llc = line-locked clock output; res = reset output (active low). handbook, full pagewidth mgc633 128 lcc 896 lcc digital delay some ms 20 to 200 m s pll-delay < 1 ms res llc resint llcint xtal ce poc v dda poc logic analog poc v ddd digital poc delay clock pll ce llc clk0 res
1998 may 15 36 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a table 5 power-on control sequence 15 output formats table 6 output formats of the vpo bus (note 1) internal power-on control sequence pin output status function directly after power-on asynchronous reset vpo15 to vpo0, rtco, rts0, rts1, gpsw, href, vref, hs, vs, llc, llc2 and cref are in high-impedance state direct switching to high impedance for 20 to 200 ms synchronous reset sequence llc, llc2, cref, rtco, rts0, rts1, gpsw and sda become active; vpo15 to vpo0, href, vref, hs and vs are held in high-impedance state internal reset sequence status after power-on control sequence vpo15 to vpo0, href, vref, hs and vs are held in high-impedance state after power-on (reset sequence) a complete i 2 c-bus transmission is required bus signal 411 (12-bit) 422 (16-bit) (2) ccir-656 (8-bit) (3) rgb (16-bit) (4) rgb (24-bit) (4) vpo15 y 07 y 17 y 27 y 37 y 07 y 17 u 07 y 07 v 07 y 17 r4 r7 r7 vpo14 y 06 y 16 y 26 y 36 y 06 y 16 u 06 y 06 v 06 y 16 r3 r6 r6 vpo13 y 05 y 15 y 25 y 35 y 05 y 15 u 05 y 05 v 05 y 15 r2 r5 r5 vpo12 y 04 y 14 y 24 y 34 y 04 y 14 u 04 y 04 v 04 y 14 r1 r4 r4 vpo11 y 03 y 13 y 23 y 33 y 03 y 13 u 03 y 03 v 03 y 13 r0 r3 r3 vpo10 y 02 y 12 y 22 y 32 y 02 y 12 u 02 y 02 v 02 y 12 g5 g7 g7 vpo9 y 01 y 11 y 21 y 31 y 01 y 11 u 01 y 01 v 01 y 11 g4 g6 g6 vpo8 y 00 y 10 y 20 y 30 y 00 y 10 u 00 y 00 v 00 y 10 g3 g5 g5 vpo7 u 07 u 05 u 03 u 01 u 07 v 07 x x x x g2 g4 r2 vpo6 u 06 u 04 u 02 u 00 u 06 v 06 x x x x g1 g3 r1 vpo5 v 07 v 05 v 03 v 01 u 05 v 05 x x x x g0 g2 r0 vpo4 v 06 v 04 v 02 v 00 u 04 v 04 x x x x b4 b7 g1 vpo3 x x x x u 03 v 03 x x x x b3 b6 g0 vpo2 x x x x u 02 v 02 x x x x b2 b5 b2 vpo1 x x x x u 01 v 01 x x x x b1 b4 b1 vpo0 x x x x u 00 v 00 x x x x b0 b3 b0 pixel order y 0123 0 1 0 1 - note 5 note 6 pixel order uv 000 -- data rates llc2 llc2 llc llc2 - i 2 c-bus control signals ofts0 = 0 ofts0 = 1 ofts0 = 1 ofts0 = 0 ofts0 = 0 ofts1 = 1 ofts1 = 0 ofts1 = 1 ofts1 = 0 ofts1 = 0 rgb888 = x rgb888 = x rgb888 = x rgb888 = 0 rgb888 = 1
1998 may 15 37 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a notes to table 5 1. vpo bus allows connection to 5 v video data bus systems. 2. values in accordance with ccir 601. 3. before and after the video data, video timing codes are inserted in accordance with ccir 656. a) vpo15 to vpo8 = vpo7 to vpo0 = ccir 656 data if i 2 c-bus bit tclo = 0 b) vpo15 to vpo8 = ccir 656 data, vpo7 to vpo0 = 3-state if i 2 c-bus bit tclo = 1. 4. during href = low rgb levels are set to 16 (10 hex). rgb 16-bit is achieved by dropping the lsbs of the 8-bit signals (after dithering if desired). 5. cref = 0 (see fig.17). 6. cref = 1 (see fig.17). fig.28 vpo output signal range with default bcs settings. equations for modification to the yuv levels via bcs control i 2 c-bus bytes brig, cont and satn. luminance: chrominance: it should be noted that the resulting levels are limited to 1 to 254 in accordance with ccir-601/656 standard. y out int cont 71 ----------------- - y128 C () brig + = uv out int satn 64 ---------------- - cr cb , 128 C () 128 + = ccir rec. 602 digital levels. a. y output range. b. u output range (cb). c. v output range (cr). handbook, full pagewidth luminance 100% + 255 + 235 + 128 + 16 0 white black u-component + 255 + 240 + 212 + 212 + 128 + 16 + 44 0 blue 100% blue 75% yellow 75% yellow 100% colourless v-component + 255 + 240 + 128 + 16 + 44 0 red 100% red 75% cyan 75% cyan 100% colourless mgc634
1998 may 15 38 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a fig.29 vbi data bypass output range. vbi data levels are not dependent on bcs settings. a. for sources containing 7.5 ire black level offset (e.g. ntsc - m). b. for sources not containing black level offset. handbook, full pagewidth luminance + 255 + 209 + 71 + 60 1 white sync bottom black shoulder black sync luminance + 255 + 199 + 60 1 white sync bottom black shoulder = black sync mgd700 fig.30 oscillator application. order number: philips 4322 143 05291. a. with quartz crystal. b. with external clock. handbook, full pagewidth xtal xtali 54 55 mgg072 xtal l = 10 m h 20% c = 10 pf c = 10 pf c = 1 nf quartz (3rd harmonic) 24.576 mhz xtali 54 55 saa7111a saa7111a
1998 may 15 39 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 16 application information fig.31 application diagram. handbook, full pagewidth q1(24.576 mhz) vpo(15 : 0) scl v ddd ai22 fei sda rtco vs hs aout gpsw rts0 rts1 res cref llc2 llc href v ss v ss v ssa v dda v ssa v dd v ss v ss vref v ss saa7111a r4 47 w c4 22 nf c7 100 nf 100 nf 100 nf 100 nf c8 c9 c11 c12 c13 c14 c15 r6 1 k w n.c. n.c. v ssa2 v sss v ss1 v ss2 v ss3 v ss4 v ss5 iicsa v ssa1 v ssa0 v dda0 v dda1 v dda2 v dd1 v dd2 v dd3 v dd4 v dd5 tms tdi tdo tck trst c17 l1 10 m h c16 1 nf 10 pf 10 pf c18 r5 1 k w 18 25 33 41 57 3 7 11 15 34 35 36 37 38 39 42 43 44 45 46 47 48 31 27 30 60 14 53 28 29 20 21 22 23 17 64 58 59 61 19 26 32 40 56 13 5 9 1 16 2 4 6 63 62 52 24 55 54 xtal xtali mgg071 v ssa bst v ss n.c. n.c. n.c. 49 50 51 100 nf 100 nf 100 nf 100 nf r3 47 w c3 22 nf v ssa ai21 r2 47 w c2 22 nf v ssa 8 ai12 r1 47 w c1 22 nf v ssa 10 ai11 12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r10 27 w r9 27 w r8 27 w r7 27 w
1998 may 15 40 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a fig.32 application diagram for rgb 24-bit output format. i 2 c-bus control bits: ofts(1 : 0) = 00 (subaddress 10h, bits d7 and d6). rgb888 = 1 (subaddress 12h, bit d3). handbook, full pagewidth oen d7 7 6 5 4 3 2 1 0 d6 d5 d4 e.g. 74hct574 d3 d2 d1 d0 44 45 46 47 48 49 50 51 31 href 17 27 30 60 28 29 53 14 20 21 32 23 v ss v ss v ss clk o7 3 r (2 : 0) r (7 : 0) o6 o5 o4 o3 o2 o1 00 v dd v dd 3 3 3 2 g (1 : 0) g (7 : 0) 3 b (2 : 0) b (7 : 0) llc2n mgg073 llc2 e.g. 74hct240 b (7 : 3) vpo (4 : 0) vpo (7 : 0) saa7111a vpo (15 : 11) r (7 : 3) g (7 : 5) g (4 : 2) vpo (10 : 8) vpo (7 : 5) 5 8 8 vref hs vs rtco rts1 rts0 gpsw aout llc cref res 8 15 14 13 12 11 10 9 8 34 35 36 37 38 39 42 43 vpo (15 : 8) 16.1 layout hints use separate ground planes for analog and digital ground. connect these planes at one point directly under the device, by using a zero w resistor. use separate supply lines for analog and digital supply. place the supply decoupling capacitors close to the supply pins. place the coupling (clamp) capacitors close to the analog input pins. place the termination resistors close to the coupling capacitors. care should be exercised concerning the hidden layout capacitors around the crystal application. to avoid reflection effects use serial resistors in the clock, sync and data lines.
1998 may 15 41 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 17 i 2 c-bus description 17.1 i 2 c-bus format table 7 write procedure table 8 read procedure (combined format) table 9 description of i 2 c-bus format notes 1. if more than one byte data is transmitted then the auto-increment of the subaddress is performed. 2. during slave transmitter mode the scl-low period may be extended by pulling scl to low (in accordance with the i 2 c-bus specification). 3. the i 2 c-bus subaddress 00 has to be initialized with 0 before being read. s slave address w ack-s subaddress ack-s data (n bytes) ack-s p s slave address w ack-s subaddress ack-s sr slave address r ack-s data (n bytes) ack-m p code description s start condition sr repeated start condition slave address w 0100 1000b (iicsa = low) or 0100 1010b (iicsa = high) slave address r 0100 1001b (iicsa = low) or 0100 1011b (iicsa = high) ack-s acknowledge generated by the slave ack-m acknowledge generated by the master subaddress subaddress byte; see table 10 data data byte; see table 10; note 1 p stop condition x = lsb slave address read/write control bit; x = 0, order to write (the circuit is slave receiver); x = 1, order to read (the circuit is slave transmitter) slave address read = 49h or 4bh; note 2 write = 48h or 4ah iicsa = 0 or 1 subaddresses 00h chip version read and write; note 3 01h reserved - 02h to 05h front-end part read and write 06h to 13h decoder part read and write 14h reserved - 15h to 17h decoder part read and write 18h to 19h reserved - 1ah to 1ch line-21 text slicer part read only 1dh to 1eh reserved - 1fh status byte read only
1998 may 15 42 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a table 10 i 2 c-bus receiver/transmitter overview note 1. all unused control bits must be programmed with logic 0. slave address read write iicsa 49h 4bh 48h 4ah 0 1 register function sub- addr d7 d6 d5 d4 d3 d2 d1 d0 chip version 00 id07 id06 id05 id04 id03 id02 id01 id00 reserved 01 (1) (1) (1) (1) (1) (1) (1) (1) analog input contr 1 02 fuse1 fuse0 gudl2 gudl1 gudl0 mode2 mode1 mode0 analog input contr 2 03 (1) hlnrs vbsl wpoff holdg gafix gai28 gai18 analog input contr 3 04 gai17 gai16 gai15 gai14 gai13 gai12 gai11 gai10 analog input contr 4 05 gai27 gai26 gai25 gai24 gai23 gai22 gai21 gai20 horizontal sync start 06 hsb7 hsb6 hsb5 hsb4 hsb3 hsb2 hsb1 hsb0 horizontal sync stop 07 hss7 hss6 hss5 hss4 hss3 hss2 hss1 hss0 sync control 08 aufd fsel exfil (1) vtrc hpll vnoi1 vnoi0 luminance control 09 byps pref bpss1 bpss0 vblb uptcv aper1 aper0 luminance brightness 0a brig7 brig6 brig5 brig4 brig3 brig2 brig1 brig0 luminance contrast 0b cont7 cont6 cont5 cont4 cont3 cont2 cont1 cont0 chroma saturation 0c satn7 satn6 satn5 satn4 satn3 satn2 satn1 satn0 chroma hue control 0d huec7 huec6 huec5 huec4 huec3 huec2 huec1 huec0 chroma control 0e cdto cstd2 cstd1 cstd0 dccf fctc chbw1 chbw0 reserved 0f (1) (1) (1) (1) (1) (1) (1) (1) format/delay control 10 ofts1 ofts0 hdel1 hdel0 vrln ydel2 ydel1 ydel0 output control 1 11 gpsw cm99 feco compo oeyc oehv vipb colo output control 2 12 rtse1 rtse0 tclo cbr rgb888 dit aosl1 aosl0 output control 3 13 vctr1 vctr0 cctr1 cctr0 bchi1 bchi0 bclo1 bclo0 reserved 14 (1) (1) (1) (1) (1) (1) (1) (1) v_gate1_start 15 vsta7 vsta6 vsta5 vsta4 vsta3 vsta2 vsta1 vsta0 v_gate1_stop 16 vsto7 vsto6 vsto5 vsto4 vsto3 vsto2 vsto1 vsto0 v_gate1_msb 17 (1) (1) (1) (1) (1) (1) vsto8 vsta8 reserved 18-19 (1) (1) (1) (1) (1) (1) (1) (1) text slicer status 1a (1) (1) (1) (1) f2val f2rdy f1val f1rdy decoded bytes of the text slicer 1b p1 byte16 byte15 byte14 byte13 byte12 byte11 byte10 1c p2 byte26 byte25 byte24 byte23 byte22 byte21 byte20 reserved 1d-1e (1) (1) (1) (1) (1) (1) (1) (1) status byte 1f sttc hlck fidt glimt glimb wipa sltca code
1998 may 15 43 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 17.2 i 2 c-bus detail the i 2 c-bus receiver slave address is 48h/49h. subaddresses 0f, 14, 18, 19, 1d and 1e are reserved; subaddress 01 is reserved for chip version. 17.2.1 s ubaddress 00 table 11 chip version sa00; note 1 note 1. x = reserved. 17.2.2 s ubaddress 02 table 12 analog control 1 sa02; note 1 notes 1. mode select (see figs 33 to 40). 2. for modes 0 to 3 use byps(sa09,d7) = 0 (chrominance trap active), for modes 4 to 7 use byps = 1 (chrominance trap bypassed). table 13 analog control 1 sa 02, d5 to d3 (see fig.14) function logic levels id07 id06 id05 id04 id03 id02 id01 id00 chip version v1 0001xxxx v2 0010xxxx function (2) control bits d2 to d0 mode 2 mode 1 mode 0 mode 0 : cvbs (automatic gain) 0 0 0 mode 1 : cvbs (automatic gain) 0 0 1 mode 2 : cvbs (automatic gain) 0 1 0 mode 3 : cvbs (automatic gain) 0 1 1 mode4:y (automatic gain) + c (gain channel 2 ?xed to gai2 level) 1 0 0 mode5:y (automatic gain) + c (gain channel 2 ?xed to gai2 level) 1 0 1 mode6:y (automatic gain) + c (gain channel 2 adapted to y gain) 1 1 0 mode7:y (automatic gain) + c (gain channel 2 adapted to y gain) 1 1 1 decimal value update hysteresis for 9-bit gain control bits d5 to d3 gudl 2 gudl 1 gudl 0 0.... off 0 0 0 ....7 7 lsb 1 1 1
1998 may 15 44 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a table 14 analog control analog function select fuse control bits d7 and d6 fuse 1 fuse 0 ampli?er plus anti-alias ?lter bypassed 0 0 01 ampli?er active 1 0 ampli?er plus anti-alias ?lter active 1 1 fig.33 mode 0; cvbs (automatic gain). handbook, halfpage ai22 ai21 ai12 ai11 chroma luma ad2 ad1 mgc637 fig.34 mode 1; cvbs (automatic gain). handbook, halfpage mgc638 ai22 ai21 ai12 ai11 chroma luma ad2 ad1 fig.35 mode 2; cvbs (automatic gain). handbook, halfpage mgc639 ai22 ai21 ai12 ai11 chroma luma ad2 ad1 fig.36 mode 3; cvbs (automatic gain). handbook, halfpage mgc640 ai22 ai21 ai12 ai11 chroma luma ad2 ad1 fig.37 mode 4 y (automatic gain) + c (gain channel 2 fixed to gai2 level). handbook, halfpage mgc641 ai22 ai21 ai12 ai11 chroma luma ad2 ad1 fig.38 mode 5 y (automatic gain) + c (gain channel 2 fixed to gai2 level). handbook, halfpage mgc642 ai22 ai21 ai12 ai11 chroma luma ad2 ad1
1998 may 15 45 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a fig.39 mode 6 y (automatic gain) + c (gain channel 2 adapted to y gain). handbook, halfpage mgc643 ai22 ai21 ai12 ai11 chroma luma ad2 ad1 fig.40 mode 7 y (automatic gain) + c (gain channel 2 adapted to y gain). handbook, halfpage mgc644 ai22 ai21 ai12 ai11 chroma luma ad2 ad1 17.2.3 s ubaddress 03 table 15 analog control 2 (aico2) sa03 function bit name logic level control bit static gain control channel 1 (gai18) (see sa04) sign bit of gain control gai18 see table 16 d0 static gain control channel 2 (gai28) (see sa05) sign bit of gain control gai28 see table 17 d1 gain control ?x (gafix) automatic gain controlled by mode 1 and mode 0 gafix 0 d2 gain control is user programmable via gai1 + gai2 gafix 1 d2 automatic gain control integration (holdg) agc active holdg 0 d3 agc integration hold (freeze) holdg 1 d3 white peak off (wpoff) white peak control active wpoff 0 d4 white peak off wpoff 1 d4 vertical blanking select (vbsl) long vertical blanking vbsl 0 d5 short vertical blanking vbsl 1 d5 hl not reference select (hlnrs) normal clamping by hl not hlnrs 0 d6 reference select by hl not hlnrs 1 d6
1998 may 15 46 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 17.2.4 s ubaddress 04 table 16 gain control analog (aic03); static gain control channel 1 gai1 sa 04, d7 to d0 17.2.5 s ubaddress 05 table 17 gain control analog (aic04); static gain control channel 2 gai2 sa 05, d7 to d0 17.2.6 s ubaddress 06 table 18 horizontal sync begin sa 06, d7 to d0 decimal value gain (db) sign bit control bits d7 to d0 gai18 gai17 gai16 gai15 gai14 gai13 gai12 gai11 gai10 0.... - 5.98 0 0 0000000 ....255 0 0 1 1111111 256.... 0 1 0 0000000 ....511 5.98 1 1 1111111 decimal value gain (db) sign bit (sa 03, d1) control bits d7 to d0 gai28 gai27 gai26 gai25 gai24 gai23 gai22 gai21 gai20 0.... - 5.98 0 00000000 ....255 0 0 11111111 256.... 0 1 00000000 ....511 5.98 1 11111111 delay time (step size = 8/llc) control bits d7 to d0 hsb7 hsb6 hsb5 hsb4 hsb3 hsb2 hsb1 hsb0 - 128... - 108 forbidden (outside available central counter range) - 107... 1 0 0 1 0101 ...108 (50hz) 0 1 1 0 1100 ...107 (60hz) 0 1 1 0 1011 109...127 (50hz) forbidden (outside available central counter range) 108...127 (60hz)
1998 may 15 47 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 17.2.7 s ubaddress 07 table 19 horizontal sync stop sa 07, d7 to d0 17.2.8 s ubaddress 08 table 20 sync control sa 08, d7 to d5, d3 to d0 delay time (step size = 8/llc) control bits d7 to d0 hss7 hss6 hss5 hss4 hss3 hss2 hss1 hss0 - 128... - 108 forbidden (outside available central counter range) - 107... 1 0 0 1 0 1 0 1 ...108 (50hz) 0 1 1 0 1 1 0 0 ...107 (60hz) 0 1 1 0 1 0 1 1 109...127 (50hz) forbidden (outside available central counter range) 108...127 (60hz) function bit name logic level control bit vertical noise reduction (vnoi) normal mode vnoi1 0 d1 vnoi0 0 d0 searching mode vnoi1 0 d1 vnoi0 1 d0 free running mode vnoi1 1 d1 vnoi0 0 d0 vertical noise reduction bypassed vnoi1 1 d1 vnoi0 1 d0 horizontal pll (hpll) pll closed hpll 0 d2 pll open, horizontal frequency ?xed hpll 1 d2 tv/vtr mode select (vtrc) tv mode (recommended for poor quality tv signals only) vtrc 0 d3 vtr mode (recommended as default setting) vtrc 1 d3 extended loop ?lter (exfil) word width of the loop ?lter (lf2) ampli?cation = 16-bit exfil 0 d5 word width of the loop ?lter (lf2) ampli?cation = 14-bit exfil 1 d5 field selection (fsel) 50 hz, 625 lines fsel 0 d6 60 hz, 525 lines fsel 1 d6 automatic ?eld detection (aufd) field state directly controlled via fsel aufd 0 d7 automatic ?eld detection aufd 1 d7
1998 may 15 48 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 17.2.9 s ubaddress 09 table 21 luminance control sa 09, d7 to d0 note 1. not to be used with bypassed chrominance trap. function bit name logic level control bit aperture factor (aper) aperture factor = 0 aper1 0 d1 aper0 0 d0 aperture factor = 0.25 aper1 0 d1 aper0 1 d0 aperture factor = 0.5 aper1 1 d1 aper0 0 d0 aperture factor = 1.0 aper1 1 d1 aper0 1 d0 update time interval for agc value (uptcv) horizontal update (once per line) uptcv 0 d2 vertical update (once per ?eld) uptcv 1 d2 vertical blanking luminance bypass (vblb) active luminance processing vblb 0 d3 luminance bypass during vertical blanking vblb 1 d3 aperture band pass (centre frequency) (bpss) centre frequency = 4.1 mhz bpss1 0 d5 bpss0 0 d4 centre frequency = 3.8 mhz; note 1 bpss1 0 d5 bpss0 1 d4 centre frequency = 2.6 mhz; note 1 bpss1 1 d5 bpss0 0 d4 centre frequency = 2.9 mhz; note 1 bpss1 1 d5 bpss0 1 d4 pre?lter active (pref) bypassed pref 0 d6 active pref 1 d6 chrominance trap bypass (byps) chrominance trap active; default for cvbs mode byps 0 d7 chrominance trap bypassed; default for s-video mode byps 1 d7
1998 may 15 49 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 17.2.10 s ubaddress 0a table 22 luminance brightness control brig7 to brig0 sa 0a 17.2.11 s ubaddress 0b table 23 luminance contrast control cont7 to cont0 sa 0b 17.2.12 s ubaddress 0c table 24 chrominance saturation control satn7 to satn0 sa 0c 17.2.13 s ubaddress 0d table 25 chrominance hue control huec7 to huec0 sa 0d offset control bits d7 to d0 brig7 brig6 brig5 brig4 brig3 brig2 brig1 brig0 255 (bright) 1 1 1 1 1 1 1 1 128 (ccir level) 1 0 0 0 0 0 0 0 0 (dark) 0 0 0 0 0 0 0 0 gain control bits d7 to d0 cont7 cont6 cont5 cont4 cont3 cont2 cont1 cont0 1.999 (maximum) 0 1 1 1 1 1 1 1 1.109 (ccir level) 0 1 0 0 0 1 1 1 1.0 01000000 0 (luminance off) 0 0 0 0 0 0 0 0 - 1 (inverse luminance) 1 1 0 0 0 0 0 0 - 2 (inverse luminance) 1 0 0 0 0 0 0 0 gain control bits d7 to d0 satn7 satn6 satn5 satn4 satn3 satn2 satn1 satn0 1.999 (maximum) 0 1 1 1 1 1 1 1 1.0 (ccir level) 0 1 0 0 0 0 0 0 0 (colour off) 0 0 0 0 0 0 0 0 - 1 (inverse chrominance) 11000000 - 2 (inverse chrominance) 10000000 hue phase (deg) control bits d7 to d0 huec7 huec6 huec5 huec4 huec3 huec2 huec1 huec0 +178.6.... 0 1 1 1 1 1 1 1 ....0.... 0 0 0 0 0 0 0 0 .... - 180 10000000
1998 may 15 50 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 17.2.14 s ubaddress 0e table 26 chrominance control sa 0e function bit name logic level control bit chroma bandwidth (chbw0 and chbw1) small bandwidth ( ? 620 khz) chbw1 0 d1 chbw0 0 d0 nominal bandwidth ( ? 800 khz) chbw1 0 d1 chbw0 1 d0 medium bandwidth ( ? 920 khz) chbw1 1 d1 chbw0 0 d0 wide bandwidth ( ? 1000 khz) chbw1 1 d1 chbw0 1 d0 fast colour time constant (fctc) nominal time constant fctc 0 d2 fast time constant fctc 1 d2 disable chrominance comb ?lter (dccf) chrominance comb ?lter on (during vref = 1) (see figs 24 and 25) dccf 0 d3 chrominance comb ?lter off dccf 1 d3 colour standard (cstd0 to cstd2); logic levels 100, 110 and 111 are reserved, do not use colour standard control automatic switching between pal bghi and ntsc m (ntsc-japan with special level adjustment; luminance brightness subaddress 0a = 95h, luminance contrast subaddress 0bh = 48h) cstd2 0 d6 cstd1 0 d5 cstd0 0 d4 colour standard control automatic switching between ntsc 4.43 (50 hz) and pal 4.43 (60 hz) cstd2 0 d6 cstd1 0 d5 cstd0 1 d4 colour standard control automatic switching between pal n and ntsc 4.43 (60 hz) cstd2 0 d6 cstd1 1 d5 cstd0 0 d4 colour standard control automatic switching between ntsc n and pal m cstd2 0 d6 cstd1 1 d5 cstd0 1 d4 colour standard control automatic switching between secam and pal 4.43 (60 hz) cstd2 1 d6 cstd1 0 d5 cstd0 1 d4 clear dto (cdto) disabled cdto 0 d7 every time cdto is set, the internal subcarrier dto phase is reset to 0 and the rtco output generates a logic 0 at time slot 68 (see rtco description fig.20). so an identical subcarrier phase can be generated by an external device (e.g. an encoder). cdto 1 d7
1998 may 15 51 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 17.2.15 s ubaddress 10 table 27 format/delay control sa 10 table 28 vref pulse position and length vrln sa 10 (d3) notes 1. additional vref positions can be achieved via i 2 c-bus bits vctr1 and vctr0 (see fig.9). 2. the numbers given in parenthesis refer to ccir line counting. table 29 fine position of hs hdel0 and hdel1 sa 10 table 30 output format selection ofts0 and ofts1 sa 10 luminance delay compensation (steps in 2/llc) control bits d2 to d0 ydel2 ydel1 ydel0 - 4... 1 0 0 ...0... 0 0 0 ...3 0 1 1 vrln vref at 60 hz 525 lines (1) vref at 50 hz 625 lines (1) 0 101 length 240 242 286 288 line number ?rst last ?rst last ?rst last ?rst last field 1 (2) 19 (22) 258 (261) 18 (21) 259 (262) 24 309 23 310 field 2 (2) 282 (285) 521 (524) 281 (284) 522 (525) 337 622 336 623 fine position of hs with a step size of 2/llc control bits d5 and d4 hdel1 hdel0 000 101 210 311 formats control bits d7 and d6 ofts1 ofts0 rgb (5, 6 and 5), rgb (8, 8 and 8) (dependent on control bit rgb888); see table 32 00 yuv 422 16 bits 0 1 yuv 411 12 bits 1 0 yuv ccir-656 8 bits 1 1
1998 may 15 52 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 17.2.16 s ubaddress 11 table 31 output control 1 sa 11 function bit name logic level control bit colour on (colo) automatic colour killer colo 0 d0 colour forced on colo 1 d0 decoder vip bypassed (vipb) dmsd data to yuv output vipb 0 d1 adc data to yuv output; dependent on mode settings vipb 1 d1 output enable horizontal/vertical sync (oehv) hs, href, vref and vs high-impedance inputs oehv 0 d2 outputs hs, href, vref and vs active oehv 1 d2 output enable yuv data (oeyc) vpo-bus high-impedance inputs oeyc 0 d3 output vpo-bus active oeyc 1 d3 inverse composite blank (compo) vref is vertical reference compo 0 d4 vref is inverse composite blank compo 1 d4 fei control (feco) fei sampling at cref = low (saa7110 compatible); (see fig.19) feco 0 d5 fei sampling at cref = high feco 1 d5 compatibility to saa7199 (cm99) default value cm99 0 d6 to be set if saa7199 (digital encoder) is used for re-encoding in conjunction with rtco cm99 1 d6 general purpose switch (gpsw) switches directly pin 64 gpsw gpsw 0 d7 gpsw 1 d7
1998 may 15 53 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 17.2.17 s ubaddress 12 table 32 output control 2 sa 12, d7 to d6, d4 to d0 function bit name logic level control bit analog test select (aosl) aout connected to internal test point 1 aosl1 0 d1 aosl0 0 d0 aout connected to input ad1 aosl1 0 d1 aosl0 1 d0 aout connected to input ad2 aosl1 1 d1 aosl0 0 d0 aout connected to internal test point 2 aosl1 1 d1 aosl0 1 d0 dithering (noise shaping) control (dit) dithering off dit 0 d2 dithering on dit 1 d2 rgb output format selection (rgb888) rgb (5, 6 and 5) rgb888 0 d3 rgb (8, 8 and 8) rgb888 1 d3 chrominance interpolation ?lter function (cbr) cubic interpolation (default) cbr 0 d4 linear interpolation (lower bandwidth) cbr 1 d4 3-state control vpo7 to vpo0 (tclo) vpo7 to vpo0 depends on oeyc, fei only (default) (see figs 18, 19 and 22) tclo 0 d5 vpo7 to vpo0 in 3-state [and ofts (1 : 0) = 3] (see tables 3 and 6) tclo 1 d5 real time outputs mode select (rtse0) odd switched to output pin 40 rtse0 0 d6 vl switched to output pin 40 rtse0 1 d6 real time outputs mode select (rtse1) plin switched to output pin 39 rtse1 0 d7 hl switched to output pin 39 rtse1 1 d7
1998 may 15 54 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 17.2.18 s ubaddress 13 table 33 output control 3 sa 13 function bit name logic level control bit bypass control low for vpo7 to vpo0 no bypass bclo1 0 d1 bclo0 0 d0 permanent bypass bclo1 0 d1 bclo0 1 d0 bypass controlled by v_gate bclo1 1 d1 bclo0 0 d0 bypass controlled by delayed v_gate bclo1 1 d1 bclo0 1 d0 bypass control high for vpo15 to vpo8 no bypass bchi1 0 d3 bchi0 0 d2 permanent bypass bchi1 0 d3 bchi0 1 d2 bypass controlled by v_gate bchi1 1 d3 bchi0 0 d2 bypass controlled by delayed v_gate bchi1 1 d3 bchi0 1 d2 clock reference output control cref is independent of vref cctr1 0 d5 cctr0 0 d4 cref is low if vref = 0 cctr1 0 d5 cctr0 1 d4 cref is high if vref = 0 cctr1 1 d5 cctr0 0 d4 cref always = 1 cctr1 1 d5 cctr0 1 d4 vertical reference output control (vref) internal vref vctr1 0 d7 vctr0 0 d6 vref_ccir vctr1 0 d7 vctr0 1 d6 programmable v_gate vctr1 1 d7 vctr0 0 d6 delayed programmable v_gate vctr1 1 d7 vctr0 1 d6
1998 may 15 55 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... 17.2.19 s ubaddress 15 table 34 start of decoded data on vpo-port sa 15; note 1 notes 1. start of decoded data on vpo-port (end of bypassed region; start of vref if selected by vctr1 and vctr0; see figs 8 and 10). 2. line numbers in brackets refer to ccir line counting. field frame line (2) counting decima l value msb (sa 17, d0) control bits d7 to d0 vsta8 vsta7 vsta6 vsta5 vsta4 vsta3 vsta2 vsta1 vsta0 50hz1st1 312100111000 2nd 314 1st 2 0.... 000000000 2nd 315 1st 312 ....310 100110111 2nd 625 60hz1st1(4)262100000110 2nd 264 (267) 1st 2 (5) 0.... 000000000 2nd 265 (268) 1st 262 (265) ....260 100000101 2nd 525 (3)
1998 may 15 56 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... 17.2.20 s ubaddress 16 t able 35 s top of decoded data on vpo- port sa 16; note 1 n otes 1. s top of decoded data on vpo- port ( begin of bypassed region ; stop of vref if selected by vctr1 and vctr0; see f igs 8 and 10). 2. l ine numbers in brackets refer to ccir line counting . 17.2.21 s ubaddress 17 table 36 sign bits of the vbi-data stream control field frame line (2) counting decimal value msb (sa 17, d0) control bits d7 to d0 vsto8 vsto7 vsto6 vsto5 vsto4 vsto3 vsto2 vsto1 vsto0 50hz1st1 312 1 00111000 2nd 314 1st 2 0.... 0 00000000 2nd 315 1st 312 ....310 1 00110111 2nd 625 60hz1st1(4)262 1 00000110 2nd 264 (267) 1st 2 (5) 0.... 0 00000000 2nd 265 (268) 1st 262 (265) ....260 1 00000101 2nd 525 (3) function bit name logic level control bit vbi-data stream start (vsta8); see sa 15 sign bit vbi-data stream start vsta8 see table 34 d0 vbi-data stream stop (vsto8); see sa 16 sign bit vbi-data stream stop vsto8 see table 35 d1
1998 may 15 57 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 17.2.22 s ubaddress 1a ( read - only register ) table 37 line-21 text slicer status sa 1a, d3 to d0 17.2.23 s ubaddress 1b ( read - only register ) table 38 first decoded data byte of the text slicer sa 1b 17.2.24 s ubaddress 1c ( read - only register ) table 39 second decoded data byte of the text slicer sa 1c 17.2.25 s ubaddress 1f ( read - only register ) table 40 status byte sa 1f i 2 c-bus status bit name function status bit f1rdy new data on ?eld 1 has been acquired (for asynchronous reading); active high d0 f1val line-21 of ?eld 1 carries valid data; active high d1 f2rdy new data on ?eld 2 has been acquired (for asynchronous reading); active high d2 f2val line-21 of ?eld 2 carries valid data; active high d3 i 2 c-bus text data bits function data bits byte1 (6 to 0) data bit 6 to 0 of ?rst data byte d6 to d0 p1 parity error ?ag bit; bit goes high when a parity error has occurred d7 i 2 c-bus text data bits function data bits byte2 (6 to 0) data bit 6 to 0 of second data byte d6 to d0 p2 parity error ?ag bit; bit goes high when a parity error has occurred d7 i 2 c-bus status bit name function status bit code colour signal in accordance with selected standard has been detected; active high d0 sltca slow time constant active in wipa-mode; active high d1 wipa white peak loop is activated; active high d2 glimb gain value for active luminance channel is limited [min (bottom)]; active high d3 glimt gain value for active luminance channel is limited [max (top)]; active high d4 fidt identi?cation bit for detected ?eld frequency; low = 50 hz, high = 60 hz d5 hlck status bit for locked horizontal frequency; low = locked, high = unlocked d6 sttc status bit for horizontal phase loop; low = tv time-constant, high = vtr time-constant d7
1998 may 15 58 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 18 filter curves 18.1 anti-alias ?lter curve 18.2 tuf-block ?lter curve fig.41 anti-alias filter. handbook, full pagewidth 6 v (db) - 42 024 68101214 f (mhz) mgd138 - 6 - 12 - 18 - 24 - 30 - 36 0 fig.42 interpolation filter for the upsampled cvbs-signal. handbook, full pagewidth 6 v (db) - 42 - 48 - 54 024 68101214 f (mhz) mgg067 - 6 - 12 - 18 - 24 - 30 - 36 0
1998 may 15 59 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 18.3 luminance ?lter curves handbook, full pagewidth f y (mhz) 18 - 30 024 8 6 mgd139 6 v y (db) - 18 - 6 (1) (2) (4) (3) (1) (2) (4) (3) fig.43 luminance control sa 09h, 4.43 mhz trap/cvbs mode, prefilter on, different aperture bandpass centre frequencies. (1) = 43h; (2) = 53h; (3) = 63h; (4) = 73h. fig.44 luminance control sa 09h, 4.43 mhz trap/cvbs mode, prefilter on, different aperture factors. (1) = 40h; (2) = 41h; (3) = 42h; (4) = 43h. handbook, full pagewidth f y (mhz) 18 - 30 024 8 6 mgd140 6 - 18 - 6 (1) (2) (3) (4) (4) (3) (2) (1) v y (db)
1998 may 15 60 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a fig.45 luminance control sa 09h, 4.43 mhz trap/cvbs mode, prefilter off, different aperture band-pass centre frequencies. (1) = 03h; (2) = 13h; (3) = 23h; (4) = 33h. handbook, full pagewidth f y (mhz) 18 - 30 024 8 6 mgd141 6 - 18 - 6 (1) (2) (4) (3) (1) (2) (4) (3) v y (db) fig.46 luminance control sa 09h, y/c mode, prefilter on, different aperture factors. (1) = c0h; (2) = c1h; (3) = c2h; (4) = c3h. handbook, full pagewidth f y (mhz) 18 - 30 024 8 6 mgd142 6 - 18 - 6 (1) (2) (3) (4) v y (db)
1998 may 15 61 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a fig.47 luminance control sa 09h, y/c mode, prefilter off, different aperture factors. (1) = 80h; (2) = 81h; (3) = 82h; (4) = 83h. handbook, full pagewidth f y (mhz) 18 - 30 024 8 6 mgd143 6 - 18 - 6 (1) (2) (3) (4) v y (db) fig.48 luminance control sa 09h, 3.58 mhz trap/cvbs mode, prefilter on, different aperture band-pass centre frequencies. (1) = 43h; (2) = 53h; (3) = 63h; (4) = 73h. handbook, full pagewidth f y (mhz) 18 - 30 024 8 6 mgd144 6 - 18 - 6 (1) (2) (4) (3) (1) (2) (4) (3) v y (db)
1998 may 15 62 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a fig.49 luminance control sa 09h, 3.58 mhz trap/cvbs mode, prefilter on, different aperture factors. (1) = 40h; (2) = 41h; (3) = 42h; (4) = 43h. handbook, full pagewidth f y (mhz) 18 - 30 024 8 6 mgd145 6 - 18 - 6 (1) (2) (3) (4) (4) (3) (2) (1) v y (db) fig.50 luminance control sa 09h, 3.58 mhz trap/cvbs mode, prefilter off, different aperture band-pass centre frequencies. (1) = 03h; (2) = 13h; (3) = 23h; (4) = 33h. handbook, full pagewidth f y (mhz) 18 - 30 024 8 6 mgd146 6 - 18 - 6 (1) (2) (4) (3) (1) (2) (4) (3) v y (db)
1998 may 15 63 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 18.4 chrominance ?lter curves 19 i 2 c-bus start set-up the given values force the following behaviour of the saa7111a: C the analog input ai11 expects a signal in cvbs format; analog anti-alias filter active C automatic field detection C yuv 4:2:2 16-bit output format enabled C outputs hs, href, vref and vs active C contrast, brightness and saturation control in accordance with ccir standards C chrominance processing with nominal bandwidth (800 khz). fig.51 chrominance filter. (1) transfer characteristics of the chrominance low-pass dependent on chbw[1 : 0] settings. chbw [1 : 0] = 00; (2) chbw [1 : 0] = 01; (3) chbw [1 : 0] = 10; (4) chbw [1 : 0] = 11. handbook, full pagewidth 2.7 6 0 - 6 - 12 - 18 - 24 - 30 - 36 - 42 - 48 - 54 0 0.54 1.08 1.62 2,16 mgd147 f (mhz) v (db) (1) (2) (3) (4) (4) (1) (3) (2)
1998 may 15 64 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a table 41 i 2 c-bus start set-up values note 1. all x values must be set to low. sub (hex) function name (1) values (bin) (hex) 76543210start 00 chip version id07 to id00; see table 9 read only 01 reserved 0 0 0 0 0 0 0 0 00 02 analog input control 1 fuse1 and fuse0, gudl2 to gudl0, mode2 to mode0 11000000 c0 03 analog input control 2 x, hlnrs, vbsl, wpoff, holdg, gafix, gai28 and gai18 00100011 33 04 analog input control 3 gai17 to gai10 0 0 0 0 0 0 0 0 00 05 analog input control 4 gai27 to gai20 0 0 0 0 0 0 0 0 00 06 horizontal sync start hsb7 to hsb0 1 1 1 0 1 0 1 1 eb 07 horizontal sync stop hss7 to hss0 1 1 1 0 0 0 0 0 e0 08 sync control aufd, fsel, exfil, x, vtrc, hpll, vnoi1 and vnoi0 10001000 88 09 luminance control byps, pref, bpss1 and bpss0, vblb, uptcv, aper1 and aper0 00000001 01 0a luminance brightness brig7 to brig0 1 0 0 0 0 0 0 0 80 0b luminance contrast cont7 to cont0 0 1 0 0 0 1 1 1 47 0c chrominance saturation satn7 to satn0 0 1 0 0 0 0 0 0 40 0d chroma hue control huec7 to huec0 0 0 0 0 0 0 0 0 00 0e chrominance control cdto, cstd2 to cstd0, dccf, fctc, chbw1 and chbw0 00000001 01 0f reserved 0 0 0 0 0 0 0 0 00 10 format/delay control ofts1 and ofts0, hdel1 and hdel0, vrln, ydel2 to ydel0 01000000 40 11 output control 1 gpsw, cm99, feco, compo, oeyc, oehv, vipb, and colo 00011100 1c 12 output control 2 rtse1 and rtse0, tclo, cbr, rgb888 dit, aosl1 and aosl0 00000001 00 13 output control 3 cctr1 and cctr0, bchi1 and bchi0, bclo1 and bclo0, vctr1 and vctr0 00000000 00 14 reserved 0 0 0 0 0 0 0 0 00 15 vbi-data stream start vsta7 to vsta0 0 0 0 0 0 0 0 0 00 16 vbi-data stream stop vsto7 to vsto0 0 0 0 0 0 0 0 0 00 17 msbs for vbi control x, x, x, x, x, x, vsto8, and vsta8 0 0 0 0 0 0 0 0 00 18-19 reserved 0 0 0 0 0 0 0 0 00 1a text slicer status 0, 0, 0, 0, f2val, f2rdy, f1val, and f1rdy read only register 1b decoded bytes of the text slicer p1, byte1 (6 to 0) 1c p2, byte2 (6 to 0) 1d-1e reserved 0 0 0 0 0 0 0 0 00 1f status byte sttc, hlck, fidt, glimt, glimb, wipa, sltca and code read only register
1998 may 15 65 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 20 package outlines unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1.0 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 95-12-19 97-08-01 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
1998 may 15 66 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.10 2.75 2.55 0.25 0.45 0.30 0.23 0.13 14.1 13.9 0.8 17.45 16.95 1.2 0.8 7 0 o o 0.16 0.10 0.16 1.60 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.03 0.73 sot393-1 ms-022 96-05-21 97-08-04 d (1) (1) (1) 14.1 13.9 h d 17.45 16.95 e z 1.2 0.8 d e q e a 1 a l p detail x l (a ) 3 b 16 y c e h a 2 d z d a z e e v m a 1 64 49 48 33 32 17 x b p d h b p v m b w m w m 0 5 10 mm scale pin 1 index qfp64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm sot393-1 a max. 3.00
1998 may 15 67 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 21 soldering 21.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 21.2 re?ow soldering reflow soldering techniques are suitable for all lqfp and qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. 21.3 wave soldering wave soldering is not recommended for lqfp and qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. caution wave soldering is not applicable for all lqfp and qfp packages with a pitch (e) equal or less than 0.5 mm. if wave soldering cannot be avoided, for lqfp and qfp packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 21.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1998 may 15 68 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a 22 definitions 23 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 24 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1998 may 15 69 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a notes
1998 may 15 70 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a notes
1998 may 15 71 philips semiconductors product speci?cation enhanced video input processor (evip) saa7111a notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1998 sca60 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors 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novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 printed in the netherlands 655102/1200/04/pp72 date of release: 1998 may 15 document order number: 9397 750 03118
go to philips semiconductors' home page select & go... start part catalog & datasheets catalog by function discrete semiconductors audio clocks and watches data communications microcontrollers peripherals standard analog video wired communications wireless communications catalog by system automotive consumer multimedia systems communications pc/pc-peripherals cross reference models packages application notes selection guides other technical documentation end of life information datahandbook system relevant links about catalog tree about search about this site subscribe to enews catalog & datasheets search saa7111a saa7111a information as of 2000 - 08 - 24 saa7111a; enhanced video input processor (evip) ? description ? features ? applications ? datasheet ? products, packages, availability and ordering ? find similar products ? pal delay line for correcting pal phase errors l real time status information output (rtco) l brightness contrast saturation (bcs) control on - chip l the yuv (ccir - 601) bus supports a data rate of: ? 864 f h = 13.5 mhz for 625 line sources ? 858 f h = 13.5 mhz for 525 line sources. l data output streams for 16, 12 or 8 - bit width with the following formats: ? yuv 4 :1 :1 (12 - bit) ? yuv 4 :2 :2 (16 - bit) ? yuv 4 :2 :2 (ccir - 656) (8 - bit) ? rgb (5, 6and 5) (16 - bit) with dither ? rgb (8, 8and 8) (24 - bit) with special application. l odd/even field identification by a non interlace cvbs input signal l fix level for rgb output format during horizontal blanking l 720 active samples per line on the yuv bus l one user programmable general purpose switch on an output pin l built - in line - 21 text slicer l a 27 mhz vertical blanking interval (vbi) data bypass programmable by i 2 pc - bus for intercast applications l power - on control l two via i 2 pc - bus switchable outputs for the digitized cvbs or y/c input signals ad1 (7 to 0) and ad2 (7 to 0) l chip enable function (reset for the clock generator and power save mode up from chip version 3) l compatible with memory - based features (line - locked clock) l boundary scan test circuit complies with the ? ieee std. 1149.1 - 1990 ? ( id - code = 0 f111 02 b) l i 2 pc - bus controlled (full read - back ability by an external controller) l low power (<0.5 w), low voltage (3.3 v), small package (lqfp64) l 5 v tolerant digital i/o ports. l desktop/notebook (pcmcia) video multimedia applications
l multimedia l digital television l image processing l video phone l intercast. please read information about some discontinued variants of this product . datasheet type nr. title publication release date datasheet status page count file size (kb) datasheet saa7111a enhanced video input processor (evip) 15-may-98 product specification 72 441 download products, packages, availability and ordering partnumber north american partnumber order code (12nc) marking/packing package device status buy online saa7111ah/02 saa7111ahbg-s 9352 327 00551 standard marking * tray dry pack, bakeable, single sot393 full production - saa7111ahbg 9352 327 00557 standard marking * tray dry pack, bakeable, multiple sot393 full production - saa7111ah/02/s5 9352 636 52557 standard marking * tray dry pack, bakeable, multiple sot393 full production - saa7111ah/03 9352 600 18551 standard marking * tray dry pack, bakeable, single sot393 full production 9352 600 18557 standard marking * tray dry pack, bakeable, multiple sot393 full production saa7111ahz/02 9352 327 10518 standard marking * reel dry pack, smd, 13" sot314 full production - SAA7111AHZBD-S 9352 327 10551 standard marking * tray dry pack, bakeable, single sot314 full production - saa7111ahzbd 9352 327 10557 standard marking * tray dry pack, bakeable, multiple sot314 full production - saa7111ahz/03 9352 600 17551 standard marking * tray dry pack, bakeable, single sot314 full production 9352 600 17557 standard marking * tray dry pack, bakeable, multiple sot314 full production find similar products:
saa7111a links to the similar products page containing an overview of products that are similar in function or related to the part number(s) as listed on this page. the similar products page includes products from the same catalog tree(s) , relevant selection guides and products from the same functional category. find similar products: copyright ? 2000 royal philips electronics all rights reserved. terms and conditions .

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